1. Technical Field
The embodiments described herein relate to a phase synchronization apparatus, and more particularly, to a Phase Locked Loop (PLL) circuit used in a semiconductor integrated circuit.
2. Related Art
In general, during implementation of a high-speed semiconductor integrated circuit (IC), as of a frequency of an external clock increases, a frequency of an internal clock also increases. Accordingly, in order to improve adaptability to a high frequency clock, semiconductor ICs are making use of PLL circuits instead of Delay Locked Loop (DLL) circuits as a clock phase synchronization apparatus. Currently, PLL circuits are being used in various fields, such as wired/wireless communication systems including RF systems, and are commonly being used as a phase adjuster, a frequency mixer, and a time dividing system.
A PLL circuit generally includes a phase detector, a charge pump, a low pass filter, a voltage controlled oscillator (VCO), and a clock divider. Here, a gain of the voltage controlled oscillator, i.e., a ratio of a control voltage transmitted through the low pass filter to an output clock, is an important factor in determining operational characteristics of a PLL circuit. A conventional PLL circuit is mainly used as a voltage controlled oscillator having a large gain, and phase fixing operations having short locking times is realized. However, the voltage controlled oscillator having the large gain is problematic in that a frequency band is sensitive to voltage variations and can be easily varied, thereby degrading operational stability. Conversely, when a voltage controlled oscillator having a small gain is used in order to overcome the problems associated with the large gain, operational stability is improved. However, the voltage controlled oscillator having the small gain is also problematic in that a locking time became longer and a usable frequency band became narrower.
As such, since operational performance of a PLL circuit is dependent upon a gain of a voltage controlled oscillator, there is no alternative but to ensure operational stability when using a voltage controlled oscillator having a large gain or ensure short locking times when using a voltage controlled oscillator having a small gain. Accordingly, for high-speed semiconductor ICs, a clock phase synchronization apparatus is required having high operational performance without the above-described problems.